The present invention relates in general to semiconductor devices, and more particularly to a method and structure for making a top-side contact to a semiconductor substrate.
In some semiconductor devices (e.g., vertically-conducting power devices), the substrate forms a bottom terminal of the device, and various techniques have been used to form a low resistance contact to the bottom terminal. FIG. 1A shows a cross-sectional view of a conventional device structure with a back-side contact. As shown, a p− region 101 is formed over a p+ substrate region 102. A conductive interconnect layer 103 formed at the bottom of the substrate is used as a back-side contact. For certain applications, it may be desirable to contact the substrate from the top-side of the device. FIGS. 1B-1C show cross-section views illustrating two conventional techniques for contacting the bottom terminal of a device through the top-side.
In FIG. 1B, a heavily doped diffused region 105 extends through p− region 101 to reach p+ substrate region 102. A conductive interconnect layer 107 is formed over diffused region 105, which together with diffused region 105 forms a top-side contact to p+ substrate region 102. In FIG. 1C, a deep trench 108 is formed through p− region 101 to reach p+ substrate region 102. Then a conductive material 109 is used to fill the trench, thus forming a top-side contact to p+substrate region 102.
Even though these conventional techniques have been used for making top-side contact to the bottom terminal, there are limitations associated with these techniques. For example, diffused region 105 in FIG. 1B requires a high temperature drive-in process after a diffusion or implant step. This leads to wide lateral out-diffusion and high thermal budget. In FIG. 1C, the process of making a deep trench and then filling it with a conductive material is often complicated. If polysilicon is used to fill the trench, it is often difficult to obtain highly doped polysilicon to form a low resistivity top-side contact.
Thus, there is a need for a technique whereby a low resistance top-side contact is made to the substrate while maintaining a simple manufacturing process.
In accordance with an embodiment of the invention, a semiconductor structure includes a starting semiconductor substrate having a recessed portion. A semiconductor material is formed in the recessed portion, and has a higher resistivity than the starting semiconductor substrate. A body region extends in the semiconductor material, and has a conductivity type opposite that of the semiconductor material. Source regions extend in the body region, and have a conductivity type opposite that of the body region. A gate electrode extends adjacent to but is insulated from the body region. A first interconnect layer extends over and is in contact with a non-recessed portion of the starting semiconductor substrate. The first interconnect layer and the non-recessed portion provide a top-side electrical contact to portions of the starting semiconductor substrate underlying the semiconductor material.
In one embodiment, the recessed portion is substantially filled with an epitaxial layer.
In still another embodiment, the semiconductor structure further includes a dielectric spacer vertically extending between the semiconductor material and a non-recessed portion of the starting semiconductor substrate.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.